The present invention relates to a semiconductor device, or more in particular to a fine-structured MOS transistor.
In order to achieve a high speed and a high integration of a device, the MOS transistor has progressed toward an ever smaller size according to the scaling rule. The scaling rule advocated by J. R. Brews, for example, permits a device to be reduced in size by decreasing the junction depth of the diffused layer and/or the thickness of the gate oxide and/or increasing the substrate doping concentration. This scaling rule is discussed in IEEE, Electron Device Letters, EDL-1, No. 1 (1980) pp. 2-4 and still provides one indicator for size reduction.
As the channel length reaches the order of 0.1 .mu.m with the miniaturization of the device, however, the parameter for miniaturization under the scaling rule reaches a physical limit. When the junction depth of the diffused layer is reduced, the contact resistance is increased. A thinner oxide film, on the other hand, causes a tunneling current. Also, an increased substrate concentration leads to variations in threshold voltage or a deteriorated cut-off characteristic. In this way, the size reduction of the conventional structure by scaling has reached its own limit.
As a method for breaking this limit of size reduction of the MOS transistor, a conventional device as described in JP-A-50-8483 is known in which that side of the gate electrode which is in contact with an insulator is embedded deeper in a semiconductor substrate than the lower side of the drain. The structure of such a device is shown in FIG. 11. When a gate electrode 15 is grooved as shown in FIG. 11 (a grooved-gate structure), the extension of a depletion layer of the drain 91 fails to reach a source 11 under the influence of the drain voltage, and therefore a punchthrough indicated by 92 which otherwise might be caused by the current flowing through the region in the depletion layer 91 not in the control of the gate electrode 15 can be suppressed, thereby realizing a device smaller in channel length 90 than a conventional transistor having a planar structure as shown in FIG. 10.
A technique for further reducing the size of a device is described in JP-A-2-94478. According to this known method, a grooved gate transistor is formed with N+ and N- diffused layers, a high melting point metal film and an insulator to suppress the punchthrough and to reduce the parasitic capacitance and the series resistance. Also, JP-A-2-101774 and JP-A-3-283670 disclose an LDD (Lightly Doped Drain-Source) structure known as a diffused layer structure for a transistor having a conventional planar structure combined with a grooved gate transistor to alleviate the electric field at the drain.
In the above-mentioned conventional grooved gate MOS transistor, although the structure can be reduced in size by suppressing the punchthrough more than the planar structure, the threshold voltage is undesirably decreased in a smaller region. FIG. 6 shows threshold voltage to channel length characteristic curves. The threshold voltage of a grooved gate MOS transistor 61, which lowers less than that of a conventional planar structure 62, decreases with a further decrease in channel length. In the short channel region resulting in lowering the threshold voltage, a punch-through current 92 flows deep in the substrate as shown in FIG. 10, and therefore the current cannot be controlled by the gate voltage so that the threshold voltage greatly vanes, thus making it impossible to obtain a normal transistor characteristic. An ideal threshold voltage characteristic, as indicated by a curve 60, is constant regardless of the channel length.
The various effects of a given shape on the threshold voltage characteristic or the various characteristics caused by a given shape have not been made clear in the prior art. The substrate concentration or doping concentration dependency is not known either.